| Title |
Updated |
Grade |
Popularity |
Size |
|
|
 IspLSI 1048C High-Density Programmable Logic |
2009-05-26 |
 |
26 |
175.81 KB |
| The ispLSI 1048C features 5-Volt in-system program-
ming and in-system diagnostic capabilities. It is the first
device which offers non-volatile reprogrammability of the
ogic, and the interconnect to provide truly reconfigurable
.. |
| |
|
| High Performance E2CMOS PLD Generic Array Logic |
2009-05-26 |
|
28 |
198.03 KB |
| The GAL18V10, at 7.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2
) floating gate technology to provide a very flexible 20-pin
PLD. CMOS circuitry allows the GAL18V10&nb.. |
| |
|
| IspLSI and pLSI 2032 High Density Program- |
2009-05-26 |
|
22 |
182.81 KB |
| The ispLSI and pLSI 2032 are High Density Program-
mable Logic Devices. The devices contain 32 Registers,
32 Universal I/O pins, two Dedicated Input Pins, three
Dedicated Clock Input Pins, one dedicated Global OE
input pin and a Global.. |
| |
|
| IspLSI 2032E High Density Programmable Logic |
2009-05-26 |
|
15 |
178.56 KB |
| The ispLSI 2032E is a High Density Programmable Logic
Device. The device contains 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedicated Global OE input pin and
a Global Routing&n.. |
| |
|
| High-Speed Asynchronous E2CMOS PLD Generic Array Logic™ |
2009-05-26 |
|
29 |
198.25 KB |
| The GAL20RA10 combines a high performance CMOS process
with electrically erasable (E2
) floating gate technology to provide
the highest speed performance available in the PLD market.
Lattice Semiconductor’s E2
CMOS circuitry achieves power.. |
| |
|
| HIGH PERFORMANCE E2CMOS PLD Technology |
2009-05-26 |
|
18 |
180.08 KB |
| The GAL20XV10 combines a high performance CMOS process
with electrically erasable (E2
) floating gate technology to provide
the highest speed Exclusive-OR PLD available in the market. At
90mA maximum Icc (75mA typical Icc), the GAL20XV.. |
| |
|
| IspLSI and pLSI 2128 High Density Program- |
2009-05-26 |
|
17 |
177.28 KB |
| The ispLSI and pLSI 2128 are High Density Program-
mable Logic Devices. The devices contain 128 Registers,
128 Universal I/O pins, eight Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a G.. |
| |
|
| 3.3V LOW VOLTAGE, ZERO POWER OPERATION |
2009-05-26 |
|
28 |
197.76 KB |
| The GAL22LV10Z and GAL22LV10ZD, at 15ns maximum propa-
gation delay time and 100µA standby current, combine 3.3V
CMOS process technology with Electrically Erasable (E2
) floating
gate technology to provide the best PLD solution to supp.. |
| |
|
| Low Voltage E2CMOS PLD Generic Array Logic™ |
2009-05-26 |
|
18 |
190.82 KB |
| The GAL26CLV12D, at 5 ns maximum propagation delay time,
provides higher performance than its 5V counterpart. The
GAL26CLV12D can interface with both 3.3V and 5V signal lev-
els. The GAL26CLV12D is manufactured using Lattice
Semi.. |
| |
|
| HIGH PERFORMANCE E2CMOS PLD Generic Array Logic™ |
2009-05-26 |
|
25 |
206.37 KB |
| The GAL26CV12, at 7.5 ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E2
) floating gate technology to provide the highest
performance 28-pin PLD available on the market. E2
&nbs.. |
| |
|
| High Density Programmable Logic |
2009-05-26 |
|
27 |
199.65 KB |
| The ispLSI 3160 is a High-Density Programmable Logic
Devices containing 320 Registers, 160 Universal I/O
pins, five Dedicated Clock Input Pins, five Output Routing
Pools (ORP) and a Global Routing Pool (GRP) which
allows complete inter-conne.. |
| |
|
| IspLSI High Density Programmable Logic |
2009-05-26 |
|
24 |
174.42 KB |
| The ispLSI 3256A is a High-Density Programmable Logic
Device containing 384 Registers, 128 Universal I/O pins,
five Dedicated Clock Input Pins, eight Output Routing
Pools (ORP) and a Global Routing Pool (GRP) which
allows complete inter-conn.. |
| |
|
| IspLSI3320 High-Density Programmable Logic |
2009-05-26 |
|
17 |
207.46 KB |
| The ispLSI 3320 is a High-Density Programmable Logic
Device containing 480 Registers, 160 Universal I/O pins,
five Dedicated Clock Input Pins, ten Output Routing
Pools (ORP) and a Global Routing Pool (GRP) which
allows complete inter-connect.. |
| |
|
| IispLSI 3448 High-Density Programmable Logic |
2009-05-26 |
|
15 |
184.78 KB |
| The ispLSI 3448 is a High-Density Programmable Logic
Device containing 672 Registers, 224 Universal I/Os, five
Dedicated Clock Inputs, 14 Output Routing Pools (ORP)
and a Global Routing Pool (GRP) which allows complete
inter-connectivity bet.. |
| |
|
| GAL6001 High Performance E2CMOS FPLA Generic Array Logic™ |
2009-05-26 |
|
18 |
196.88 KB |
| Using a high performance E2
CMOS technology, Lattice
Semiconductor has produced a next-generation programmable
logic device, the GAL6001. Having an FPLA architecture, known
for its superior flexibility in state-machine design, the GAL6.. |
| |
|
| GAL6002 High Performance E2CMOS FPLA Generic Array Logic™ |
2009-05-26 |
|
18 |
206.36 KB |
| Having an FPLA architecture, the GAL6002 provides superior
flexibility in state-machine design. The GAL6002 offers the
highest degree of functional integration, flexibility, and speed
currently available in a 24-pin, 300-mil package.&nb.. |
| |
|
| ispLSI and pLSI 1032E |
2009-05-21 |
|
23 |
212.88 KB |
| Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
—.. |
| |
|
| ispLSI 1048E High-Density Programmable Logic |
2009-05-21 |
|
22 |
217.19 KB |
| • HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Twelve Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small.. |
| |
|
| 16LV8 Low Voltage E2 Generic Array Logic™ |
2009-05-21 |
|
21 |
265.74 KB |
| • HIGH PERFORMANCE E2
CMOS® TECHNOLOGY
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 2.5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 16V8 AR.. |
| |
|
| 16LV8ZD Low Voltage, Zero Power E2 Generic Array Logic™ |
2009-05-21 |
|
26 |
278.52 KB |
| • 3.3V LOW VOLTAGE, ZERO POWER OPERATION
— JEDEC Compatible 3.3V Interface Standard
— Interfaces with Standard 5V TTL Devices
—50µA Typical Standby Current (100µA Max.)
— 45mA Typical Active Current (55mA Max.)
— Dedi.. |
| |
|
| 16V8ZZD Zero Power E2 in Lattice |
2009-05-21 |
|
22 |
226.73 KB |
| • ZERO POWER E2
CMOS TECHNOLOGY
— 100µA Standby Current
— Input Transition Detection on GAL16V8Z
— Dedicated Power-down Pin on GAL16V8ZD
— Input and Output Latching During Power Down
• HIGH PERFORMANCE E2
CMOS .. |
| |
|
| 20LV8 Low Voltage E2 Generic Array Logic™ |
2009-05-21 |
|
22 |
231.15 KB |
| • HIGH PERFORMANCE E2
CMOS® TECHNOLOGY
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 2.5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
— TTL-Compatible Balanced 8mA O.. |
| |
|
| 20LV8ZD Low Voltage, Zero Power E2 Generic Array Logic™ |
2009-05-21 |
|
23 |
238.6 KB |
| • 3.3V LOW VOLTAGE, ZERO POWER OPERATION
— JEDEC Compatible 3.3V Interface Standard
— Interfaces with Standard 5V TTL Devices
—50µA Typical Standby Current (100µA Max.)
— 45mA Typical Active Current (55mA Max.)
— Dedi.. |
| |
|
| 20V8 High Performance E2 Generic Array Logic™ |
2009-05-21 |
|
29 |
352.49 KB |
| The GAL20V8C, at 5ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2
) floating gate technology to provide the highest speed
performance available in the PLD market. High spee.. |
| |
|
| 20V8ZZD Zero Power E2 in Lattice |
2009-05-21 |
|
23 |
246.33 KB |
| The GAL20V8Z and GAL20V8ZD, at 100 µA standby current and
12ns propagation delay provides the highest speed and lowest
power combination PLD available in the market. The
GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad-
van.. |
| |
|
| GAL22LV10 Low Voltage E2 Generic Array Logic™ |
2009-05-21 |
|
49 |
218.04 KB |
| The GAL22LV10D, at 4 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL22LV10C can interface with both 3.3V and 5V
signal levels. The GAL22LV10 is manufactured using Latt.. |
| |
|
| GAL22V10 High Performance E2 Generic Array Logic™ |
2009-05-21 |
|
28 |
265.09 KB |
| The GAL22V10, at 4ns maximum propagation delay time, combines
a high performance CMOS process with Electrically Erasable (E2
)
floating gate technology to provide the highest performance avail-
able of any 22V10 device on the market.&n.. |
| |
|
| ispLSI 3256E High Density Programmable Logic |
2009-05-21 |
|
19 |
208.14 KB |
| The ispLSI 3256E is a High Density Programmable Logic
Device containing 512 Registers, 256 Universal I/O pins,
five Dedicated Clock Input Pins, 16 Output Routing Pools
(ORP) and a Global Routing Pool (GRP) which allows
complete inter-connect.. |
| |
|
| In-System Programmable SuperWide™ High Density PLD |
2009-05-21 |
|
18 |
257.84 KB |
| The ispLSI 5000V Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
Outputs from the GLB.. |
| |
|
| ispLSI 6192 Cell-Based PLDs |
2009-05-21 |
|
26 |
256.45 KB |
| Lattice Semiconductor’s
new ispLSI
®
6192 Cell-Based
PLD architecture is being
acclaimed as the next wave in
the evolution of PLDs. Once
again, Lattice, the inventor of
the low-density E2
CMOS® GAL®
and In-System Programm.. |
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