| Title |
Updated |
Grade |
Popularity |
Size |
|
|
 DFT-Optimized Design Sub-Methodology |
2009-04-16 |
 |
53 |
439.55 KB |
| The Need for DFT-Optimized Design
Manufacturing test is performed by patterns automatically generated by ATPG (Automatic Test Pattern Generation) tools. To operate effectively, these tools require that the circuits be correctly designed for tes.. |
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| Using the cdc false path Constraint |
2009-04-15 |
|
42 |
31.27 KB |
| Introduction
This application note describes the use model of the cdc_false_path
constraint in the SpyGlass® Clock-Reset solution.
The cdc_false_path constraint is used by the following rules:
Syntax
The cdc_false_path constraint allows.. |
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|
| Metastability Analysis in Dynamic Verification Flow |
2009-04-15 |
|
116 |
47.23 KB |
| Introduction
This application note describes the use model of the monitors generated for
metastability analysis using the SpyGlass®-CDC solution.
Policy: Clock Reset
License Requirements: Advanced CDC License
Defin.. |
| |
|
| Generating Compatible Waivers |
2009-04-15 |
|
31 |
36.4 KB |
| Introduction
Rule messages keep on changing across SpyGlass releases. As a result, the
waiver files of previous release may become incompatible for use in the current
release. To make them compatible in the current release, use the
-gen_comp.. |
| |
|
| Handling Messages for IP Blocks |
2009-04-15 |
|
35 |
51.64 KB |
| Introduction
A typical user requirement related to IP Blocks instantiated in the HDL designs
is to report only those SpyGlass® rule messages that relate to hookup of the IP
Block instances and not report the messages that relate to logic .. |
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|
| Clock Crossing Synchronization Using Pattern Matching |
2009-04-15 |
|
50 |
40.18 KB |
| Clock Crossing Synchronization
The SpyGlass® Clock-Reset solution checks for synchronization status of
clock crossing using the following standard synchronization schemes:
2-Flop Synchronization Scheme
Cell Synchron.. |
| |
|
| GuideWareTM Reference Methodology |
2009-04-15 |
|
73 |
1883.2 KB |
| 1 GuideWare Reference Methodology – The Need
The Atrenta SpyGlass tool suite is an industry standard for early design closure in IC design flows. SpyGlass tools analyze design intent (RTL, netlist & constraints) as soon as it is captured a.. |
| |
|
| Waivers Support in SDE |
2009-04-13 |
|
36 |
194.81 KB |
| Overview
Starting with SpyGlass® 3.9.0, the features of "Waivers" and "Filters" have
been unified. In previous releases of SpyGlass, two different mechanisms,
namely "Waivers" and "Filters", were used to essentially perform the same
func.. |
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