| Title |
Updated |
Grade |
Popularity |
Size |
|
|
 Flash Memory System Builder User’s Guide |
2009-04-01 |
 |
41 |
653.35 KB |
| Note: FlashROM is available only for IGLOO, IGLOOe, ProASIC3, and ProASIC3E devices.
IGLOO/e and ProASIC3/E devices have a flexible programming option. The FlashROM and the FPGA core fabric can be
programmed independently of each other, allowi.. |
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|
| ChipEditor v6.3 User’s Guide |
2009-04-01 |
|
32 |
307.84 KB |
| ChipEditor (non-MVN)
ChipEditor is a graphical application for viewing and assigning I/O and logic macros. This tool is particularly useful when you need maximum control over your design placement.
Note: ChipEditor supports only the SX, MX, 32.. |
| |
|
| Designer Documentation Catalog |
2009-04-01 |
|
41 |
50.43 KB |
| Designer User’s Guide Provides information about using Designer for design implementation. Use Designer and its components to import
files, compile, layout, and run the floorplanning, timing, and power analysis tools.
MultiView Navigator User.. |
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|
| Designer v8.0 User’s Guide |
2009-04-01 |
|
25 |
1482.79 KB |
| Welcome to Designer
The Designer interface offers both automated and manual flows, with the push-button flow achieving the optimal solution in the
shortest cycle.
The basic steps to implement your design are:
• Starting a new design
&.. |
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|
| Design Constraints v8.0 User’s Guide |
2009-04-01 |
|
130 |
1455.07 KB |
| Design Constraints Overview
Design constraints are usually either requirements or properties in your design. You use constraints to ensure that your design meets
its performance goals and pin assignment requirements.
The Designer software sup.. |
| |
|
| Innoveda eProduct Designer Interface Guide |
2009-04-01 |
|
29 |
1103.19 KB |
| The Mentor Graphics eProduct Designer Interface Guide contains information about using the Innoveda eProduct Designer CAE software tools with the Actel Designer Series FPGA development software tools to create designs for Actel devices. Refer to.. |
| |
|
| Innoveda eProduct Designer Interface Guide |
2009-04-01 |
|
31 |
410.52 KB |
| Document Assumptions
This document assumes the following:
1. You have installed the Designer Series software in the "C:\Actel" directory.
2. You have installed the eProduct Designer software in .. |
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|
| FlashPoint User's Guide v8.0 |
2009-04-01 |
|
27 |
1042.17 KB |
| Semantics
Each custom serialization file has only one type of data format (binary, decimal, Hex or ASCII text). For example, if a file contains
two different data formats (i.e. binary and decimal) it is considered an invalid file.
The length .. |
| |
|
| FlashPro User’s Guide v6.0 |
2009-04-01 |
|
51 |
5882.56 KB |
| About FlashPro v6.0
FlashPro v6.0 is Actel's new, redesigned programming software tool for the Flash family of devices (ProASIC, ProASICPLUS,
ProASIC3/E, and Fusion). You will be able to navigate easily through the FlashPro software because of.. |
| |
|
| Flash Memory System Builder User’s Guide |
2009-04-01 |
|
29 |
1019.24 KB |
| Introduction to SmartGen
The SmartGen software generates a large variety of commonly used functions. You can create a workspace and generate structural netlists in EDIF, VHDL, and Verilog. Furthermore, you can generate VHDL and Verilog behavior.. |
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|
| SmartGen Cores Reference Guide |
2009-04-01 |
|
48 |
1436.14 KB |
| The Sklansky Adder enables you to clear the Automatic Max. Fanout check box and specify a value
for max fanout. This makes SmartGen perform logic replication on high-fanout nets so that the
maximum fanout for all the nets in the design is not .. |
| |
|
| Actel HDL Coding Style Guide |
2009-04-01 |
|
47 |
2861.24 KB |
| VHDL and Verilog* HDL are high level description languages for system and circuit design. These languages support various abstraction levels of design, including architecture-specific design. At the higher levels, these languages can be used for.. |
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|
| Antifuse Macro Library Guide for Software v8.0 |
2009-04-01 |
|
21 |
1972.06 KB |
| CC-Module Flip Flops
These macros are useful in some radiation hostile applications. They sacrifice
area in exchange for a lower single-event upset (SEU) rate caused by ion
particle collisions. These special cells use two combinational module.. |
| |
|
| MultiView Navigator v8.0 User’s Guide |
2009-04-01 |
|
32 |
2927.24 KB |
| MultiView Navigator (MVN)
Overview
MultiView Navigator is the physical design viewing and editing interface for the Fusion, ARM-enabled Fusion, IGLOO/e,
ProASIC3/E, ARM-enabled ProASIC3/E, ProASIC PLUS, Axcelerator, ProASIC, SX-A, and eX fami.. |
| |
|
| NetlistViewer (non-MVN) v6.3 User's Guide |
2009-04-01 |
|
28 |
500.03 KB |
| NetlistViewer (non-MVN)
The NetlistViewer tool displays the contents of the design as a schematic, making it easier for you to debug your design. Use this tool to view nets, ports, and instances and to trace signals. Used with PinEditor, ChipEd.. |
| |
|
| Macro Library Guide for Software v8.0 |
2009-04-01 |
|
129 |
1114.52 KB |
| Functional Description
The Fusion datasheet, available at http://www.actel.com/techdocs/ds/default.aspx, contains a detailed functional
description of the entire Analog System Builder.
Connecting Analog Ports
Each analog port must be connect.. |
| |
|
| ProASIC and ProASICPLUS Macro Library Guide |
2009-04-01 |
|
44 |
425.8 KB |
| The A500K and APA combinational cells implement all basic logic functions and have
the following features:
• Inversion available on all inputs.
• Optimized for synthesis applications.
Naming Conventions for Combinational Cells
N.. |
| |
|
| PinEditor (non-MVN) v6.3 User’s Guide |
2009-04-01 |
|
25 |
672.33 KB |
| PinEditor (non-MVN)
PinEditor is a graphical application for assigning I/O ports to package pins.
Note: PinEditor (non-MVN) supports only the SX, MX, 3200DX, ACT3, ACT2, and ACT1 families. If you are designing for other, newer families, use Pi.. |
| |
|
| SmartPower User’s Guide v8.0 |
2009-04-01 |
|
22 |
918.33 KB |
| Displays a breakdown of power consumption in the design. You can specify whether to see the power breakdown by type of component or by voltage rail using the drop-down list box.
When you select By Type from the drop-down list, the Summary tab g.. |
| |
|
| SmartTime v8.0 User’s Guide |
2009-04-01 |
|
30 |
3837.64 KB |
| Setting SmartTime Options
With SmartTime, you can:
Browse through your design’s various clock domains to examine the timing paths and identify those that violate your timing
requirements
Add and modify timing requirements and exceptions
.. |
| |
|
| Timer User’s Guide v7.2 |
2009-04-01 |
|
31 |
612.95 KB |
| Welcome to Timer
Timer is the Actel static timing analysis tool. Timing analysis is a convenient and thorough method of analyzing, debugging, and validating the timing performance of a design. This is achieved by breaking down the design into s.. |
| |
|
| VHDL VITAL™Simulation Guide |
2009-04-01 |
|
70 |
274.93 KB |
| This VHDL Vital Simulation Guide contains information about using the ModelSim and Cadence NC-V'HDL to simulate designs for Actel devices. Refer to the Designer User's Guide for additional information about using the Designer software. Refer to .. |
| |
|
| Using the Prelayout Checker |
2009-04-01 |
|
25 |
321.92 KB |
| The Verilog Simulation Guide contains information about interlacing the Designer Series FPGA development software with Verilog simulation tools. Refer to the Designer online help for additional information about using the Designer software. Refe.. |
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