| Title |
Updated |
Grade |
Popularity |
Size |
|
|
 ispLSI and pLSI 1016 High-Density Program- |
2009-05-28 |
 |
18 |
144.06 KB |
| The ispLSI and pLSI 1016 are High-Density Program-
mable Logic Devices containing 96 Registers, 32
Universal I/O pins, four Dedicated Input pins, three
Dedicated Clock Input pins and a Global Routing Pool
(GRP). The GRP provides comple.. |
| |
|
| ispLSI and pLSI 1016E High-Density |
2009-05-28 |
|
16 |
161.31 KB |
| The ispLSI and pLSI 1016E are High-Density
Programmable Logic Devices containing 96 Registers,
32 Universal I/O pins, four Dedicated Input pins, three
Dedicated Clock Input pins, one Global OE input pin and
a Global Routing Pool (GRP). The G.. |
| |
|
| ispLSI and pLSI 1032 High-Density Program- |
2009-05-28 |
|
26 |
148.44 KB |
| The ispLSI and pLSI 1032 are High-Density Program-
mable Logic Devices containing 192 Registers, 64
Universal I/O pins, eight Dedicated Input pins, four Dedi-
cated Clock Input pins and a Global Routing Pool (GRP).
The GRP .. |
| |
|
| GAL16VP8 High-Speed E2CMOS PLD Generic Array Logic™ |
2009-05-28 |
|
17 |
141.64 KB |
| The GAL16VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control appli-
cations. The GAL16VP8 is manufactured using Lattice
Semiconductor's advanced E2
CMOS process which comb.. |
| |
|
| 1000 and 1000E Family Introduction |
2009-05-28 |
|
20 |
167.88 KB |
| The ispLSI
® 1000E devices are functional supersets of
the ispLSI 1000 devices and are architecturally similar
except that the 1000E family features two new global
output enable pins per device (only one for the 1016E)
and programmable .. |
| |
|
| ispLSI 2032V/LV High Density Programmable |
2009-05-28 |
|
17 |
157.6 KB |
| The ispLSI 2032V/LV are High Density Programmable
Logic Devices that can be used in both 3.3V and 5V
systems. The devices contain 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedi.. |
| |
|
| ispLSI and pLSI 2064 High Density Program- |
2009-05-28 |
|
15 |
172.87 KB |
| The ispLSI and pLSI 2064 are High Density Program-
mable Logic Devices. The devices contain 64 Registers,
64 Universal I/O pins, four Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Rou.. |
| |
|
| ispLSI 2064V High-Density Programmable Logic |
2009-05-28 |
|
14 |
138.35 KB |
| The ispLSI 2064V is a High-Density Programmable Logic
Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Glo.. |
| |
|
| ispLSI and pLSI 2096 High Density Program- |
2009-05-28 |
|
19 |
151.82 KB |
| The ispLSI and pLSI 2096 are High Density Program-
mable Logic Devices. The devices contain 96 Registers,
96 Universal I/O pins, six Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Rout.. |
| |
|
| ispLSI 2096E High Density Programmable Logic |
2009-05-28 |
|
19 |
154.69 KB |
| The ispLSI 2096E is a High Density Programmable Logic
Device. The device contains 96 Registers, 96 Universal
I/O pins, eight Dedicated Input pins, three Dedicated
Clock Input pins, two dedicated Global OE input pins and
a Global Routin.. |
| |
|
| ispLSI 2096V High-Density Programmable Logic |
2009-05-28 |
|
17 |
149.57 KB |
| The ispLSI 2096V is a High-Density Programmable Logic
Device containing 96 Registers, six Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provide.. |
| |
|
| GAL20VP8 High-Speed E2CMOC PLD Generic Array Logic™ |
2009-05-28 |
|
23 |
141 KB |
| The GAL20VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control appli-
cations. The GAL20VP8 is manufactured using Lattice
Semiconductor's advanced E2
CMOS process which comb.. |
| |
|
| ispLSI 2128E High Density Programmable Logic |
2009-05-28 |
|
16 |
149.6 KB |
| The ispLSI 2128E is a High Density Programmable Logic
Device. The device contains 128 Registers, 128 Univer-
sal I/O pins, eight Dedicated Input pins, three Dedicated
Clock Input pins, two dedicated Global OE input pins and
a Global Routing&.. |
| |
|
| ispLSI 2128V High Density Programmable Logic |
2009-05-28 |
|
18 |
148.7 KB |
| The ispLSI 2128V is a High Density Programmable Logic
Device available in 128 and 64 I/O-pin versions. The
device contains 128 Registers, eight Dedicated Input
pins, three Dedicated Clock Input pins, two dedicated
Global OE input pins .. |
| |
|
| ispLSI 3192 High Density Programmable Logic |
2009-05-28 |
|
18 |
159.37 KB |
| The ispLSI 3192 is a High Density Programmable Logic
Device containing 384 Registers, 192 Universal I/O pins,
five Dedicated Clock Input Pins, twelve Output Routing
Pools (ORP), and a Global Routing Pool (GRP) which
allows complete inter-con.. |
| |
|
| Bar Code Reader |
2009-05-28 |
|
26 |
143.45 KB |
| The Universal Product Code was first implemented by
the grocery industry in 1973 as a method for improving
inventory control and checkout times. As its benefits
were realized, it soon spread throughout the retail indus-
try. UPC Versio.. |
| |
|
| 16V8 High Performance E2CMOS PLD |
2009-05-19 |
|
30 |
395.18 KB |
| The GAL16V8, at 3.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2
) floating gate technology to provide the highest speed
performance available in the PLD market. High sp.. |
| |
|
| 5K/8K Macro Library Supplement |
2009-05-19 |
|
17 |
1412.27 KB |
| This Preface contains information on the following topics:
n Purpose and Scope
n Documentation Conventions
n Quick Macro Reference Table.The 5K/8K Macro Library Supplement documents the features, capabilities, and use
of the library macros p.. |
| |
|
| ispLSI 6192 High Density Programmable Logic |
2009-05-19 |
|
27 |
499.6 KB |
| The ispLSI 6192 device is a High Density, Cell-Based
Programmable Logic Devices that contain a dedicated
Memory Module, a dedicated Register/Counter Module
and an 8000-gate general-purpose Programmable Logic
block. Output Routing Pools (ORP).. |
| |
|
| ispEXPERT ABEL Design Manual |
2009-05-19 |
|
24 |
642.69 KB |
| This manual provides information on ABEL-HDL design sources, hierarchical
structure, compiling, and design considerations. It is assumed that you have a basic
understanding of ABEL-HDL design.This manual contains the following information:
1&.. |
| |
|
| ABEL-HDL Reference Manual |
2009-05-19 |
|
29 |
1584.46 KB |
| ABEL-HDL is a hierarchical logic description language. ABEL-HDL design
descriptions are contained in an ASCII text file in the ABEL Hardware Description
Language, ABEL-HDL. The requirements for ABEL-HDL are described in this
manual. |
| |
|
| Avoid The Pitfalls Of High-Speed Logic Design |
2009-05-19 |
|
25 |
390.13 KB |
| Modern high-speed systems demand modern highspeed logic families. Consequently, semiconductor houses have developed such product lines as ACT, FACT, and AS. But these systems also demand that the lay-out of their boards conform tawith the result.. |
| |
|
| Learn The Fundamentals Of Digital Filter Design |
2009-05-19 |
|
30 |
469.23 KB |
| Historically, designers often have taken an analog approach to filtering. Filters were constructed using operational amplifiers, resistors, and capacitors. One op amp could implement a second-order filter, and higher-order filters could be imple.. |
| |
|
| Schematic Entry Reference Manual |
2009-05-19 |
|
17 |
754.33 KB |
| This manual provides a detailed explanation of the Symbol Editor, Schematic Editor,
and Hierarchy Navigator commands. The following topics are discussed:
1 Purpose and Scope
2 Documentation Conventions
3 Quick Command Reference |
| |
|
| ispEXPERT Compiler User Manual |
2009-05-19 |
|
46 |
952.4 KB |
| The ispEXPERT™ Compiler software (referred to as ispEXPERT) is used to optimize,
partition, place, and route logic designs for the Lattice Semiconductor in-system
programmable Large Scale Integrated (ispLSI
®) devices.
This user ma.. |
| |
|
| ispEXPERT Compiler with Viewlogic Software |
2009-05-19 |
|
102 |
611.56 KB |
| Lattice has linked high-level Verilog and VHDL with its In-
System Programmable logic devices, the two hottest
product technologies in system design today, in the new
ispEXPERT Compiler with Viewlogic. This complete
solution greatly im.. |
| |
|
| ispGDX Development System User Manual |
2009-05-19 |
|
46 |
602.36 KB |
| The ispGDX devices provide a solution for programmable signal interconnection that
can arbitrarily route signals between any two pins on the devices in a more or less
static configuration (signal paths do not change unless the device is .. |
| |
|
| ispGDX Generic Digital Crosspoint Devices |
2009-05-19 |
|
40 |
430.19 KB |
| The ispGDX family is an exciting new
series of in-system programmable
Generic Digital Crosspoint devices
from Lattice Semiconductor. Unlike
traditional CPLDs and FPGAs, this
new family has been designed to
provide unprecedented performance.. |
| |
|
| 5K/8K Macro Library Supplement |
2009-02-13 |
|
19 |
1412.27 KB |
| Purpose and Scope
The 5K/8K Macro Library Supplement documents the features, capabilities, and use
of the library macros provided with the pLSI and ispLSI Development System from
Lattice Semiconductor Corporation (LSC) to implement on LSC 800.. |
| |
|
| ABEL Design Manual |
2009-02-13 |
|
23 |
642.69 KB |
| What is in this Manual
This manual contains the following information:
n Introduction to ABEL-HDL design
n Hierarchical design in ABEL-HDL
n ABEL-HDL compiling
n ABEL-HDL design considerations
Where to Look for Information
Chapter 1, ABEL.. |
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