| Title |
Updated |
Grade |
Popularity |
Size |
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|
 Starting Active-HDL |
2010-03-17 |
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21 |
3775.38 KB |
| Installation
The installation of the Active-HDL system is invoked automatically by running the setup.exe program from the CD-ROM drive after you put the installation CD. The Install Shield Wizard that assists you in the installation process wil.. |
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| OVL QUICK REFERENCE |
2010-03-17 |
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20 |
21.54 KB |
| TYPE NAME PARAMETERS PORTS DESCRIPTION
Single-Cycle assert_always #(severity_level, property_type, msg, coverage_level) (clk, reset_n, test_expr) test_expr must always hold
Two Cycles assert_always_on_edge #(severity_level, edge_type, property.. |
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| Designed for development of VHDL, |
2010-03-17 |
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23 |
11895.73 KB |
| All Active-HDL component tools are embedded into an integrated graphical environment referred to as the framework that provides communication channels among them. Each of the tools is implemented in a separate window. By default, most of the win.. |
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| Accellera Standard OVL V2 Library Reference Manual |
2010-03-17 |
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293 |
995.69 KB |
| Notational Conventions
The following textual conventions are used in this manual:
Syntax statements appear in sans-serif typeface as shown here. In syntax statements, words in
italics are meta-variables. You must replace them with relevant li.. |
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| Supported Verilog PLI Routines |
2010-03-17 |
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16 |
131.66 KB |
| tf_add_long()
Formal Definition:
Adds two 64-bit integers.
Complete description: Language Reference Manual §24.4
Simplified Syntax:
void tf_add_long(&aof_low1, &aof_high1, low2, high2)
int *aof_low1, *aof_high1;
&nb.. |
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| PSL Reference Guide |
2010-03-17 |
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27 |
215.4 KB |
| Definition
For Sequence S:
The FL property S! holds on a given path iff there exists a prefix of the path on which S holds tightly.
The FL property S holds on a given path iff either there exists a prefix of the path on which S holds .. |
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| Active-HDL Release notes |
2010-03-17 |
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22 |
208.36 KB |
| Mixed-Simulation
An issue that resulted in a runtime error during simulation of mixed VHDL-Verilog design with SLP acceleration enabled was fixed. (SPT20594)
A problem with instantiating VHDL entities in a SystemVerilog testbench that .. |
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| Active-HDL Zuken CADSTAR Release notes |
2010-03-17 |
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25 |
209.18 KB |
| The following changes and improvements to VHDL simulation are also available:
The -g and -G arguments for asim (i.e. the arguments that assign generic values) can now be used to assign values whose type is an array of arrays (e.g. an array .. |
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| Active-HDL Lattice Release notes |
2010-03-17 |
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32 |
110.16 KB |
| The design verification based on SystemVerilog, OVA, and PSL assertions has been enhanced. The simulator can now detect and report vacuous evaluations and extra evaluations. The following assertion:
property p;
@(posedge clk ) a |-&.. |
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| Active-HDL QuickLogic Designer Edition Lite Release notes |
2010-03-17 |
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13 |
111.26 KB |
| Compiler and Simulator
NOTE: Due to internal changes in the compiler and simulator as well as updates in third-party tool libraries, all user-defined libraries should be re-compiled after the installation of Active-HDL 8.2. The installation pro.. |
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| Active-HDL Standard |
2010-03-17 |
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13 |
20.81 KB |
| Package STANDARD predefines a number of types, subtypes and functions. An implicit context clause naming this package is assumed to exist at the beginning of each design unit. Package STANDARD may not modified by the user.
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| Active-HDL Textio |
2010-03-17 |
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16 |
22.07 KB |
| The Textual Input and Output (TextIO) package contains declarations of types and subprograms that support reading from and writing to formatted text files. These text files are ASCII files of any desired format that is supported by a host comput.. |
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| Active-HDL Code Coverage Tutorial |
2010-03-17 |
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15 |
102.73 KB |
| Introduction
With the growing complexity of today's designs, testing the validity of HDL designs becomes increasingly difficult. Designers have to answer the question of whether or not the design was fully tested, which basically means if all s.. |
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| VHDL Configurations Tutorial |
2010-03-17 |
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23 |
327.3 KB |
| Introduction
In VHDL, an entity is bound to a single architecture and this association is done by means of the default bindings. However, designers often use several implementations for selected parts of a project making the default binding mec.. |
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| State Machine Entry and Debugging Tutorial |
2010-03-17 |
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25 |
334.02 KB |
| Introduction
State machine editors allow simple and easy graphical design entry. Since the state machine designs can be easily retargeted to any devices, the state editors are becoming very popular with designers who value technological indepen.. |
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| Mixed VHDL-Verilog Tutorial |
2010-03-17 |
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21 |
407.33 KB |
| Introduction
The focus of this tutorial is to get you acquainted with ability of Active-HDL to mix VHDL and Verilog descriptions in a single project.
1. After starting the Active-HDL environment, the Getting Started window appears. Select .. |
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| Post Simulation Debug Tutorial |
2010-03-17 |
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21 |
234.27 KB |
| Introduction
Post Simulation Debug is a very useful feature that allows you to simulate a project in the "off-line" mode (without a connection to the simulator). This tutorial shows how to prepare data for Post Simulation Debug and conduct simu.. |
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| Server Farm Installation Tutorial |
2010-03-17 |
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15 |
330.78 KB |
| Introduction
Server Farm is a network that allows one or more users to run their tasks in a distributed hardware/software environment. At least one computer in the network is distinguished as the Farm Controller, which is a machine .. |
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| VHDL Testbench Tutorial |
2010-03-17 |
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17 |
276.04 KB |
| The purpose of this advanced testbench tutorial is to acquaint you with methods of automatic generation of WAVES-based testbenches. The basic testbench tutorial, which you are assumed to have already gone through, deals with the single process t.. |
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| VHDL Entry and Simulation Tutorial |
2010-03-17 |
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13 |
1166.68 KB |
| The focus of this tutorial is to familiarize you with the creation cycle of designs based on the VHDL language. This tutorial is based on freq_meter design shipped with Active-HDL environment. Though some of the files are initially created using.. |
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| Active-HDL Glitches and Delta Cycle Handling |
2010-03-17 |
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8 |
94.38 KB |
| Introduction
This chapter describes how Active-HDL handles glitches and delta cycles. The purpose of this document is to familiarize you with the terminology, basic simulation procedure and means for finding causes of glitches. Active-HDL provi.. |
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| Active-HDL Locating X values with xtrace |
2010-03-17 |
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8 |
94.4 KB |
| Introduction
X values can be the source of unexpected outputs of the tested module. Active-HDL provides xtrace - a command-line utility that allows you to detect X or U values when they first appear, before they are propagated to the output por.. |
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| Active-HDL Macro Language Reference |
2010-03-17 |
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8 |
94.38 KB |
| Verilog Compilation and Simulation
An issue with incorrect evaluation of a Verilog expression was resolved. (SPT21287)
Incremental compilation of Verilog sources (alog -incr) increased the size of library files on disk even when the co.. |
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| Active-HDL Online Documentation |
2010-03-17 |
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8 |
94.38 KB |
| Active-HDLTM is an integrated environment designed for development of VHDL, Verilog/SystemVerilog, EDIF, and SystemC designs. It comprises of several design entry tools, VHDL and Verilog compiler, single simulation kernel, several standard and a.. |
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| Verilog Language Reference Guide |
2010-03-17 |
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8 |
177.4 KB |
| Built-in Primitives
Formal Definition
The built-in primitives provide a means of gate and switch modeling.
Complete description: Language Reference Manual section § 7.1.
Simplified Syntax
For and, nand, or, nor, xor, xnor, .. |
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| Timing Diagrams for Accellera Standard OVL V2.1 |
2010-03-15 |
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21 |
651.64 KB |
| OVL Release History and Major Changes
v2.0-Beta, April 2007
ovl_<checker> modules (not documented here)
enable input & fire output (tied low in beta)
clock_edge, reset_polarity & gating_type parameters
17 new ovl_<.. |
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| Handel-C Language Reference |
2010-03-15 |
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23 |
784.32 KB |
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Since Handel-C is based on the syntax of conventional C, programs written in Handel-C are implicitly sequential. Writing one command after another indicates that those instructions should be executed in that exact order. To execute instr.. |
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| OVA Reference Guide |
2010-03-15 |
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14 |
69.45 KB |
| Conventions
The following conventions are used in the description of OVA constructs.
An underline indicates an item to be substituted by the user, for example.
entity ::=
clocked_entity
| unclocked_ent.. |
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| OVL QUICK REFERENC |
2010-03-15 |
|
24 |
64.45 KB |
| YPE NAME PARAMETERS PORTS DESCRIPTION
Single-Cycle ovl_always #(severity_level, property_type, msg, coverage_level) (clock, reset, enable, test_expr, fire) test_expr must always hold
Two Cycles ovl_always_on_edge #(severity_level, edge_type, p.. |
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| Aldec SIGNED Type |
2010-03-15 |
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15 |
23.13 KB |
| The SIGNED type is a one-dimensional unconstrained array whose elements are of type STD_LOGIC . The SIGNED type is interpreted as a binary number in 2's complement notation. The leftmost array's element value is interpreted as a sign bit of a bi.. |
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