| Title |
Updated |
Grade |
Popularity |
Size |
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|
 Bind Key Summary nTrace - Hierarchy Browser Pane and Source Code Pane |
2010-06-17 |
 |
30 |
307.94 KB |
| Key alone Go to the beginning
of the line.
Go to the end of the
line.
Double-click on the
selected object.
Alt +
Ctrl + Go to the beginning
of the module.
Go to the end of the
module.
Ctrl + Shift Mark to the top of the
.. |
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|
| Novas Bookshelf |
2010-06-17 |
|
27 |
40.62 KB |
| The following books are provided by SpringSoft. Please select the desired
document.
Novas Installation & System Administration Guide
Verdi and Siloti Command Reference Manual
Verdi and Siloti Quick Reference Guide
Linking Novas Files w.. |
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| NOVAS-CDC Correlation |
2010-06-17 |
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26 |
70.27 KB |
| Convergence
Different start registers are converged to a point and then stop at the same end
register.
Figure: Convergence Before Synchronizer
Figure: Convergence After Synchronizer
Divergence
One start register diverges to .. |
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| Installation and System Administration Guide |
2010-06-17 |
|
72 |
394.49 KB |
| Overview
Workstation Requirements
Before installing the Verdi and Siloti systems, verify that you have the following
components:
• Software CD-ROM, 8mm/4mm tape, or the software files from the Internet.
• 3.7 GB hard drive spac.. |
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| Linking Novas Files with Simulators and Enabling FSDB Dumping |
2010-06-17 |
|
631 |
941.75 KB |
| FSDB Format
The Verdi system supports an open file format called Fast Signal Database
(FSDB) that has the following advantages over the standard VCD file format:
• An FSDB file is more compact than a standard VCD file. Typically, an
.. |
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| linking_dumping_pre-2010 |
2010-06-17 |
|
123 |
1819.64 KB |
| |
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| nAnalyzer User’s Guide and Tutorial Novas Verification Enhancement Solutions |
2010-06-17 |
|
50 |
5940.19 KB |
| Overview
In the area of timing analysis debug, the nAnalyzer module supports two primary
functions: viewing and analyzing Standard Delay Format (SDF) data in the
context of the design and debugging timing analysis results.
Standard Delay F.. |
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| nCompare User’s ManualNovas Verification Enhancement Solutions |
2010-06-17 |
|
80 |
2913.92 KB |
| cmpSetTypeVar
Description
Allows user to define type variables for name mapping.
Syntax
cmpSetTypeVar varname \
([%d]STRING | [%d]INTEGER | [%d]HIERARCHY | CHAR) \
[-'%c'] [-INTEGER] [+EMPTY]
Arguments
varname.. |
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| nECO User’s Guide and Tutorial Novas Verification Enhancement Solutions |
2010-06-17 |
|
38 |
2230.29 KB |
| Overview
Designers of complex chips find many reasons to modify the netlist. Often these
changes come late in the design process where errors are very costly. Netlist
changes are error-prone because the netlist is large, complex, unfamiliar.. |
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| Verdi and Siloti Command Reference Manual Novas Verification Enhancement Solutions |
2010-06-17 |
|
22 |
36591.67 KB |
| Verdi
The Verdi system includes the following primary components. With the
exception of the nCompare module which has its own document, each
component has its own chapter in this manual.
Refer to the Utilities chapter for details on the Ve.. |
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| Novas Open KDB Reference Manual |
2010-06-17 |
|
16 |
2835.29 KB |
| Overview
This chapter gives an introduction to four Open KDB models: Language models,
npiVerilog and npiVHDL, Netlist mode, npiNetlist and Source Code model,
npiSourceCode, and also explains the TCL interfaces to acc.. |
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| Verdi and Siloti Quick Reference Guide |
2010-06-17 |
|
454 |
279.53 KB |
| Automatic Tracing of Value with Verdi’s
Temporal Flow View
1. In nTrace or nWave windows, find a signal that you want to
debug.
2. Select the signal.
3. Click the Auto Trace toolbar icon .
Alternatively,
• Right-click to .. |
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| Verdi and Siloti Command Reference Manual |
2010-06-17 |
|
12 |
36591.67 KB |
| The Novas Verification Enhancement Solution, of which the Verdi
TM Automated
Debug System and the Siloti™ Visibility Automation System are a part, is an
advanced solution for debugging your digital designs that increases design
prod.. |
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| Siloti User’s Guide and Tutorial |
2010-06-17 |
|
42 |
1968.88 KB |
| The Siloti™ Visibility Automation System speeds up simulation by eliminating
the overhead associated with recording signal values and by enabling full
visibility of design activity based on a relatively small amount of signal data
ca.. |
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| Novas Symbol Library Developer's Guide |
2010-06-17 |
|
33 |
3308.42 KB |
| Use Symbol Libraries
Two environment variables specify the symbol library you want to use and where
it is located.
NOVAS_LIBS
NOVAS_LIBS specifies Novas symbol libraries you want to use for your design.
You can specify multiple libraries .. |
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| NOVAS-Synchronizer Template |
2010-06-17 |
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22 |
190.38 KB |
| Template Types
For single bit data propagating between asynchronous clock domains, the
synchronizer is used to reduce the probability for the ToDomain to sample a
meta-stability value. In such cases, the synchronizer could be simple.
For b.. |
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| Novas Command LanguageNovas Verification Enhancement Solutions |
2010-06-17 |
|
77 |
5781.82 KB |
| schClkExtractCDSetClockRoot
Description
Set the specified clock source as the clock source root in the Clock Domains
window.
Syntax
schClkExtractCDSetClockRoot [-src "clock source list"] [-dump]
Argument
-src "clock source list"
Specify.. |
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| Verdi User’s Guide and Tutorial Novas Verification Enhancement Solutions |
2010-06-17 |
|
22 |
19471.44 KB |
| Multiple-port Static RAM
Enter the following commands to start the tutorial:
1. Change to the demo directory:
% cd <working_dir>/demo/verilog/memory_demo/mport
2. Start the Verdi system:
% verdi –play demo.cmd
Create a .. |
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| Verdi User’s Guide and Tutorial Novas Verification Enhancement Solutions |
2010-06-17 |
|
10 |
19471.44 KB |
| Overview
The Verdi
TM Automated Debug System is an advanced solution for debugging
your digital designs that increases design productivity with complex System-on-
Chip (SoC), ASIC, and FPGA designs. Traditional debug tools rely on structura.. |
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| Novas-Verdi 2009.07 Enhancements and Bug Corrections |
2010-06-14 |
|
249 |
146.49 KB |
| SPS0131763 lose created bus with periods in name when reload fsdb or restore saved signal
SPS0159466 [BA] crash during behavior analysis
SPS0162369 [Verdi 2009.04][BA] verdi crash during behavior analysis
SPS0168143 .. |
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| Novas-Verdi 2009.10 Enhancements and Bug Corrections |
2010-06-14 |
|
191 |
174.46 KB |
| Bug ID Headline
SPS0111760 Novas Support Inquiry ---#(`include) error while compiling SV rtl
SPS0152895 Allows mulitiple prefix filters for get signal window
SPS0170344 syn2SymDB crash with 2009.07 R&D build
S.. |
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| Novas-Verdi 2010.01 Enhancements and Bug Corrections |
2010-06-14 |
|
269 |
119.16 KB |
| Bug ID Headline
SPS0101567 module instantiation on separate lines confuses compiler
SPS0117670 Show SV interface members with "." delimiter, not "/"
SPS0118463 Horizontal scroll bar doesn't access beginning of time .. |
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| Novas-Verdi 2010.04 Enhancements and Bug Corrections |
2010-06-14 |
|
244 |
102.63 KB |
| SPS0192961 [ius6.1_vhpi][IUS_62/92 NEW PLI]IUS FSBD dumping ERROR VPI EXPRWFC
SPS0193035 crash on loading the design
SPS0193130 Verdi freezed when restoring SaveSignal file
SPS0193327 add standard prefix to SKIP_FOR.. |
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| Novas-Siloti 2009.07 Enhancements and Bug Corrections |
2010-06-14 |
|
23 |
48.87 KB |
| Bug ID Headline
SPS0150417 ESA crashed
SPS0150551 SystemVerilog keyword used as signal name
SPS0152208 PLI crash by a long argument
SPS0160131 BA crash during ESA on Full Chip RTL model
SPS0169140 Pa.. |
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| Novas-Siloti 2009.10 Enhancements and Bug Corrections |
2010-06-14 |
|
17 |
30.59 KB |
| Bug ID Headline
SPS0173081 Turn on DE_REAL as default
SPS0173713 [M:SPS0169817] [Siloti 2009.01][DE] incorrect expanding value for buses using signed
extension rules
SPS0130411 add standard prefix to all environme.. |
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| fixed_prob_Siloti201001 |
2010-06-14 |
|
23 |
32.77 KB |
| |
| |
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| Novas-Siloti 2010.04 Enhancements and Bug Corrections |
2010-06-14 |
|
25 |
33.72 KB |
| Bug ID Headline
SPS0118122 NF on packed record in index access (in full dump)
SPS0151711 Mismatched signal if the Verilog part of the design is compiled with -sv
SPS0152551 Missing Module Name of fsdbexpand fsdb
S.. |
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| Novas-FSDB Dumper Known Problems and Limitations |
2010-06-14 |
|
23 |
25.05 KB |
| 1 Notes
This document lists the known issues and limitations related to the new re-architected dumpers
available from Novas 2010.01.
2 Essential Signal Dumping
2.1 Note for using SKIP_CELL_INSTANCE
If SKIP.. |
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| Novas-FSDB Dumper Known Problems and Limitations |
2010-06-14 |
|
424 |
169.71 KB |
| 3.1.5 Should Set FSDB Minimal Time Unit for Mixed Verilog/VHDL Design
When linking the ius?.?_vhpi dumping object directories, the FSDB minimal time unit in a mixed
Verilog/VHDL design should be set explicitly. Otherwise, the minimal t.. |
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| Novas-Language Support with Known Problems and Limitations |
2010-06-14 |
|
202 |
124.19 KB |
| 2 SystemVerilog/SVA/SVTB
All constructs, as described in the SystemVerilog IEEE 1800-2005 reference manual at
http://www.ieee.org, are supported with the following limitations. Novas supports the same SVA
sub-set as VCS 7.2 fro.. |
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