| Title |
Updated |
Grade |
Popularity |
Size |
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|
 PS2 Controller |
2009-04-07 |
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64 |
195.96 KB |
| Transmission from Controller to PS/2 device
For the Host microcontroller to send a command to the PS/2 device via the PS2 Controller, the Strobe pin must be taken high for at least one period of the external system clock signal (on the CLK inpu.. |
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| Putting Signal Integrity in its Place |
2009-04-07 |
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34 |
146.11 KB |
| in the past tracks on a circuit board could be effectively considered as simple connections. Newer logic families and faster clock speeds have undermined this basic assumption.
Fast signal edge rales in modern digital designs and the introducti.. |
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| Re-targeting the design to the Production Board |
2009-04-07 |
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31 |
227.11 KB |
| Using signal integrity simulation to uncover problems in a completed board design before any prototyping is undertaken can reduce the number of prototype iterations needed to complete a project. However, the addition of new components late in th.. |
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| Shortcut Keys |
2009-04-07 |
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51 |
127.49 KB |
| Project Panel and Platform Left-Click Double Lett-Click Right-Click Ctrl + F4 Alt + F4 Ctrl + Tab Drag & Drop in the Panel from
* one project to another
* File Explorer to Design Explorer
Ctrl + Drag & Drop from one project to another.. |
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| Situs Autorouting Essentials |
2009-04-07 |
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44 |
162.13 KB |
| The Situs Topological Router brings a new approach to the autorouting challenge, it uses advanced topological mapping to first define the routing path, then calls on a variety of proven routing algorithms to convert this 'human-like' path to a h.. |
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| Specifying the PCB Design Rules and Resolving Violations |
2009-04-07 |
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25 |
102.53 KB |
| Design rules are not a frill or an add-on for serious PCB designers—they are an integral part of the design process. Accordingly, DXP's design rule checks have been developed to interact with your style of design work.
Once upon a time t.. |
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| SRL0 Serial Port Unit |
2009-04-07 |
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33 |
193.71 KB |
| The only difference between Mode 2 and Mode 3 is that the baud rate Is variable in Mode 3. Either the internal baud rate generator or the additional Timer Unit can be used to specify the baud rate.
In all four operational modes, any instruction.. |
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| Tips for Design Capture |
2009-04-07 |
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36 |
129.56 KB |
| Placement Stages________________________________________
All objects in your design must undergo two placement stages. The first is when you activate the placement procedure for any object. At this point, the object hangs upon the cursor, waiti.. |
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| TMR3 Dual Timer Unit |
2009-04-07 |
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18 |
178.45 KB |
| Timer B overflow
Bit 7 (TFB) of the TCON register will be set under the following conditions:
• if Timer B is in either mode 0 or mode 1 and register THB has reached the overflow state.
• &.. |
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| Topological Autorouting |
2009-04-07 |
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28 |
134.6 KB |
| Early aulorouters mapped a design space by defining a set, regular grid over the entire board, the objectives being to have each component pin lying directly on a grid point and to include sufficient grid points in the free space to route all th.. |
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| Transferring a Design from Protel 99 SE |
2009-04-07 |
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163 |
127.71 KB |
| Components
As you examine your design documents in DXP, you will discover some changes—none of which should interrupt your wonx flow. One is that all text fields and part fields in schematic components and libraries are converted to parameters.. |
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| TSK165x RISC MCU |
2009-04-07 |
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17 |
593.57 KB |
| Note that in the block diagram in Figure 10:
• The size of the RAM block depends on the TSK165x variant
- 16bytesforTSK165A
- 64 bytes for TSK165B and TSK165C
• With respect t.. |
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| TSK51x MCU |
2009-04-07 |
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20 |
614.13 KB |
| External Data memory
The TSK51x Microcontroller core incorporates the Harvard architecture, with separate program (code) and data spaces:
• The code from external Program memory is fetched by strobing the PSRD pin.
.. |
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| TSK80x MCU |
2009-04-07 |
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23 |
851.45 KB |
| CPU Registers - overview
All registers in The TSKSOx can be changed under program conirol. They can be split into three groups, as described below.
The first group consists of two duplicate sets of 8-bit registers - base and alternative. Only .. |
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| Updating the NanoBoard Firmware |
2009-04-07 |
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31 |
199.7 KB |
| Downloading the new firmware__________________________
The configuration for the Xilinx Serial PROM device is stored in a PROM file, using the Intel MCS-86 format. This is an ASCII hex file with extension racs.
To download the new configuratio.. |
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| Utilizing the NanoBoard Flash Memory |
2009-04-07 |
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22 |
322.3 KB |
| Running the Flash Memory Controller
The procedure for loading an embedded software file into the Flash RAM can be carried out at any time - with or without an FPGA project open and irrespective of whether a design has currently been programmed .. |
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| VGA Controller |
2009-04-07 |
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36 |
205.03 KB |
| While the value in the horizontal counter (HCOUNT) is less than the total number of viewable pixels in a line (Pixiotai, the integer value of DISPSIZE_H). the counter is incremented on the rising edge of the external clock signal {CLK). Pixel ad.. |
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| Working with a Version Control System |
2009-04-07 |
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17 |
259.45 KB |
| You can interface directly between DXP and popular third party version control systems (VCS), including Visual SourceSafe®. You can add an entire project or individual documents within a project to your VCS.
This tutorial uses the Visual So.. |
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| Working with Altera Devices and Place and Route Tools |
2009-04-07 |
|
104 |
222.99 KB |
| For advanced users, the default Quartus TCL (TCLQ) script file can be configured for advanced settings using the Def auitScript_Quartus. Tx- file located in the \Altium2004\Syscem folder The Altera project can be opened in Quartus if required.
.. |
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| Working with Simulation Waveforms |
2009-04-07 |
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20 |
134.04 KB |
| waveforms are scaled by the same amount, such thai all the waveforms are visible, and the largest waveform almost fills the window. The X direction will be scaled according to setting for that type of analysis. For example, the total range of th.. |
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| Working with Xilinx Devices and Place and Route Tools |
2009-04-07 |
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40 |
247.48 KB |
| This stage invokes the Xilinx NGDBuiid tool, translating the EDIF output from the FPGA project synthesis process to a Xilinx Native Genenc Database (NGD) file and Xilinx Project Navigator project (NPL) file, in this process, a logic design rule .. |
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| Bootstrapping the Daughter Board FPGA |
2009-03-30 |
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157 |
227.65 KB |
| Verification of download to Flash Memory
After ycu have doMvoaded the FPGA programming file to the Flash RAM device, a check shou'C be made to ensure the megrifyoftheprogrammngfe. Tocoths. from the Frssrt RAM Contmffet for FFGA Boorcacg click c.. |
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| CAMtastic Apertures |
2009-03-30 |
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109 |
276.73 KB |
| PCB layers are createc from photographic t m which has been exposes to light. Apertures 3te :he physical open "gs through which the light sh nes on the f-m. CAM caia includes aperture def«tions ■size andsh3pet plus instructions about w*-*.. |
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| CAMtastic Feature Highlights |
2009-03-30 |
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252 |
108.53 KB |
| One of the essent a steps in 'he development ana manufacture of an electronic product is the fabrication of "he PCB. Tine to market pressures demand lhat the PC3 design is transferred from PCB ayout t*-cue.* *■: fa: Icatic" rap dly 3nd error fr.. |
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| CAMtastic Introduction |
2009-03-30 |
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194 |
127.24 KB |
| CAMtastic offers a variety of tools: the most basic of which are for viewing and editing CAM data. Once image and drill files have been imported, CAMtastic can receive instructions determining layer types and stacKup, at which point a netlist ca.. |
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| CAMtastic Panels for Fabrication and Assembly |
2009-03-30 |
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60 |
523.13 KB |
| Traditionally, design engineers have used CAM tools for verification only, visually reviewing their Gerber and Drill outputs before forwarding these files to the fabrication house. Experienced designers will, however, acknowledge the importance .. |
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| CAMtastic Reverse Engineering PCBs |
2009-03-30 |
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228 |
152.46 KB |
| After importing CAM data, you will notice that one of the Export options remains grayed-out, regardless of which CAMtastic editor you're in: Export to PCB. This command allows you to reverse-engineer a PCB layout directly from CAM files. This do.. |
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| Component, Model and Library Concepts |
2009-03-30 |
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17 |
120.26 KB |
| Components are the basic building blocks of an electronic product. During the design capture and implementation processes, components need to be represented in different ways: as logical symbols on the schematic, as footprints (decals) on the PC.. |
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| Connectivity and Multi-Sheet Design |
2009-03-30 |
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39 |
992.1 KB |
| These eight nodes are eligible for inclusion in a bus because they have net labels that share the same prefix, followed by a numenc suffix. The logical bus is created by a net label with the syntax D[0..7], where D is the shared prefix, and the .. |
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| Design Portability, Configurations and Constraints |
2009-03-30 |
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23 |
280.93 KB |
| The design tor an FPGA is captured in a set of schematic and/cr VHDL source f es. As ive-- as Pie symbols, wirrtg and VHDL source that makes up the design. there is ether essential information that must be captured.
This can be broadly labeled .. |
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