| Title |
Updated |
Grade |
Popularity |
Size |
|
|
 ADE XL Simulation in Cadence |
2009-09-23 |
 |
84 |
23346.06 KB |
| ADE_XL_Simulation |
| |
|
| ES SKILL Interface with audio |
2009-09-23 |
|
37 |
17083.52 KB |
| ES_SKILL_Interface_with_audio |
| |
|
| Setting Constraints in Cadence |
2009-09-23 |
|
73 |
13023.07 KB |
| SettingConstraints |
| |
|
| What's Thumbs in Cadence |
2009-09-23 |
|
35 |
21.5 KB |
| Thumbs |
| |
|
| Virt Analog Placer in Cadence |
2009-09-23 |
|
48 |
19209.78 KB |
| VirtAnalogPlacer_V3 |
| |
|
| Virt Cell Planner in Cadence |
2009-09-23 |
|
33 |
24413.28 KB |
| VirtCellPlanner_V2 |
| |
|
| Virtuoso Lsyout Optimizer |
2009-09-23 |
|
39 |
13670.55 KB |
| VLO_V3 |
| |
|
| Cadence® Library Path Editor User Guide |
2009-03-07 |
|
69 |
248.81 KB |
| Setting Up cds.lib Files
You have a choice of methods for initially setting up a cds.lib file:
Using the Cadence-supplied cds.lib file as a base
Building a completely new cds.lib file with the Library Path Editor
Creating a cds.lib fil.. |
| |
|
| Cell Design Tutorial |
2009-03-07 |
|
71 |
2031.48 KB |
| Getting Started with the Cadence
Software
In this chapter, you learn about the Cadence® software environment and the Virtuoso® layout
editor as you do the following tasks:
Copying the Tutorial Database on page 12
Starting the Ca.. |
| |
|
| Virtuoso® Schematic Composer User Guide |
2009-03-07 |
|
223 |
3714.49 KB |
| Understanding Connectivity and Naming
Conventions
Connectivity is the way in which components and pins are linked together in a nonambiguous
manner. The connectivity in a schematic is represented by wires linking the component pins
to other .. |
| |
|
| Virtuoso® Schematic Composer Tutorial |
2009-03-07 |
|
56 |
767.21 KB |
| If you are using an installed tutorial that other people have used, you need to reset the files.
See Running the Installation Script on page 11.
Prerequisites
Before you can install the tutorial database, either the Virtuoso® schematic co.. |
| |
|
| Timing Library Format Reference |
2009-03-07 |
|
153 |
2193.28 KB |
| Introduction
A timing library format (TLF) file is organized into two major scopes: the library scope and the
cell scope.
Library-scope entries contain administrative information including vendor, technology
used, as well as global models .. |
| |
|
| Dracula® Reference |
2009-03-07 |
|
404 |
6541.27 KB |
| The purpose of this chapter is to provide an introduction to the Dracula® standalone physical
verification product.
This chapter focuses primarily on the following:
“Introducing Dracula” on page 31
“Introducing Hierarchical Dracul.. |
| |
|
| Dracula® User Guide |
2009-03-07 |
|
373 |
1865.93 KB |
| Interfaces to Dracula
The Dracula® standalone verification product offers a suite of software applications for
Integrated Circuit (IC) design verification.
Overview of This Chapter
This chapter contains the following sections.
Using C.. |
| |
|
| IEEE Standard Verilog® Hardware Description Language |
2009-03-07 |
|
303 |
2942.22 KB |
| Introduction
(This introduction is not part of IEEE Std 1364-2001, IEEE Standard Verilog
®
Hardware Description Language.)
The Verilog
¤
Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE
Std 1364-199.. |
| |
|
| Cadence® NC-Verilog® Simulator Help |
2009-03-07 |
|
3426 |
9279.14 KB |
| Getting Help
This chapter contains the following sections:
About Online Help
Getting Help on Commands to Run Tools
Getting Help on Simulator Commands
Getting Help on Tool Messages
Related Manuals and Specifications and Other Docu.. |
| |
|
| Cadence NC-Verilog Simulator Tutorial |
2009-03-07 |
|
2445 |
342.59 KB |
| This tutorial introduces you to the Cadence NC-Verilog simulator and SimVision.
The example used in the tutorial is a design for a drink dispensing machine written in the
Verilog hardware description language. Using this example, you will lear.. |
| |
|
| Simulation Environment Help™ |
2009-03-07 |
|
136 |
575.02 KB |
| Setting Up SE Help
In this chapter, you can find information about
“About SE Help” on page 9
“Finding the Information You Want” on page 10
“Before You Can Run a Simulation” on page 11
“Displaying the Simulation Menu” on page.. |
| |
|
| Envisia™ Silicon Ensemble™ Place-and-Route Reference |
2009-03-07 |
|
88 |
4556.54 KB |
| The Envisiaä Silicon Ensemble äplace-and-route software is a complete system that can perform all
the complex tasks needed to create the physical layout of an integrated circuit. This chapter introduces
you to the following aspects o.. |
| |
|
| Technology File Known Problems and Solutions |
2009-03-07 |
|
142 |
96.54 KB |
| PCR 158888: Layer property types not supported
Description: The technology file does not support the following layer property types:
ILExpr
NLPExpr
hierProp
Solution: Do not use these layer property types.
PCR 173447: Edit Layers pro.. |
| |
|
| Design Data Translator’s Reference |
2009-03-07 |
|
593 |
2093.08 KB |
| Overview of the Translators
This chapter describes the following:
Overview on page 16
Understanding the Translators on page 16
How to Start the Translators on page 18
Overview
The Cadence® Design Framework II environment is t.. |
| |
|
| Cadence® Verilog®-AMS Language Reference |
2009-03-07 |
|
247 |
1910.73 KB |
| Preface
This manual describes the analog and mixed-signal aspects of the Cadence® Verilog®-AMS
language. With Verilog-AMS, you can create and use modules that describe the high-level
behavior and structure of analog, digital, and mixe.. |
| |
|
| Verilog® In for Design Framework II™ User Guide and Reference |
2009-03-07 |
|
152 |
527.13 KB |
| About This Manual
This manual contains reference information about Verilog® In, which you can use to import a
design from Verilog Hardware Description Language (HDL) format into a Design Framework
II™ database format.
Finding Infor.. |
| |
|
| Printing Instructions—Labs SKILL Development of Parameterized Cells 4.4.6 |
2009-03-06 |
|
57 |
177.9 KB |
| Lab 2-2 Using ROD in a SKILL Procedure
Objective: This exercise demonstrates how to use ROD
constructs in a SKILL procedure to create simple
physical structures.
In this exercise you define a SKILL procedure that uses a ROD construct to
cre.. |
| |
|
| Printing Instructions—Lecture Training Manual |
2009-03-06 |
|
34 |
156.08 KB |
| 2. Select ROD Introduction—Execute code and observe what
happens in the layout editor window.
Is the resulting object similar to the initial collection of rectangles?
In what ways is it different?
3. Select the new object and move it to a d.. |
| |
|
| SKILL Development of Parameterized Cells Lab Book |
2009-03-06 |
|
223 |
792.68 KB |
| Before You Begin Module 2 Labs
The exercises in this lab have been specially streamlined to reduce the
amount of typing required. When you start the
Cadence® Design Framework II software, a Virtuoso® Layout Editor
window appears. The.. |
| |
|
| SKILL Development of Parameterized Cells Lab Book Table of Contents |
2009-03-06 |
|
68 |
54.06 KB |
| Lab 1-1 No Labs for this Module .................................................................................................. 1-1
Chapter 2 Introduction to Relative Object Design
Lab 2-1 Creating Aligned Rectangles ......................... |
| |
|
| SKILL Development of Parameterized Cells Training Manual |
2009-03-06 |
|
623 |
766.77 KB |
| Audience
This course is primarily for layout designers, especially those interested in
programmatic cell development.
Prerequisites:
n Hands-on experience with Design Framework II and Virtuoso Layout Editor
n Familiarity with SKILL
n Exper.. |
| |
|
| SKILL Development of Parameterized Cells Training Manual Table of Contents |
2009-03-06 |
|
57 |
55.06 KB |
| Chapter 1 Introduction
Audience .......................................................................................................................... 1-3
Agenda ............................................................................... |
| |
|
| SKILL Development of Parameterized Cells Training Manual Version 4.4.6 |
2009-03-06 |
|
112 |
24045.28 KB |
| How Pcells Function
A submaster cell resides in virtual memory for the duration of your editing session and is
accessible by all cellviews. When you create an instance in a cellview, and a submaster with
the same parameter values already exis.. |
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